RESEARCHER PROFILE
Nihar R. Mohapatra
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Indian Institute of Technology Gandhinagar
Nihar R. Mohapatra works in Advancements in Semiconductor Devices and Circuit Design, Semiconductor materials and devices, Low-power high-performance VLSI design, Analog and Mixed-Signal Circuit Design, Radio Frequency Integrated Circuit Design. Recorded institutional associations include Indian Institute of Technology Gandhinagar.
152Publications
1,071Citations
13H-index
Inclusion identifies researchers whose recorded research contributions may inform their university’s understanding of its research community. It does not rank individual research quality or establish current employment.
Selected research works
Up to 100 highly cited works; DOI links open the original research. Counts reflect the collected record, not real-time citation totals.
Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET
2017 · 224 citationsThe effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance
2002 · 92 citationsModeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors
2003 · 78 citations32nm high-density high-speed T-RAM embedded memory technology
2010 · 20 citationsComprehensive Analysis of Sheet Thickness Scaling on the Performance of Nanosheet nFETs
2024 · 18 citationsA Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors
2021 · 17 citationsUnified Theory of the Capacitance Behavior in LDMOS Devices
2021 · 17 citationsModeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs
2016 · 15 citationsSource Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors
2019 · 15 citationsA Complementary RF-LDMOS Architecture Compatible with 0.13μm CMOS Technology
2006 · 14 citationsDetailed analysis of FIBL in MOS transistors with high-k gate dielectrics
2003 · 14 citationsA Bottom-Up Scalable Compact Model for Quantum Confined Nanosheet FETs
2021 · 14 citationsParasitic Capacitance in Nanosheet FETs: Extraction of Different Components and Their Analytical Modeling
2024 · 14 citationsFast and accurate lithography simulation using cluster analysis in resist model building
2015 · 13 citationsCHISEL programming operation of scaled nor flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
2003 · 13 citationsPBTI in HKMG nMOS Transistors— Effect of Width, Layout, and Other Technological Parameters
2017 · 13 citationsModeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors
2017 · 13 citationsVariability sources in nanoscale bulk FinFETs and TiTaN- a promising low variability WFM for 7/5nm CMOS nodes
2019 · 13 citationsGradient Error Compensation in SC-MDACs
2020 · 13 citationsEffects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis
2020 · 13 citationsScalable Substrate Current Model for LDMOS Transistors Based on Internal Drain Voltage
2022 · 13 citationsIntegration of high-performance SiGe:C HBTs with thin-film SOI CMOS
2005 · 12 citationsThe impact of channel engineering on the performance and reliability of LDMOS transistors
2005 · 11 citationsCompact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs
2017 · 11 citationsAnalog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis
2019 · 11 citations