RESEARCHER PROFILE

Luis Entrena

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L

Universidad Carlos III de Madrid

Radiation Effects in ElectronicsVLSI and Analog Circuit TestingPhysical Unclonable Functions (PUFs) and Hardware SecurityEmbedded Systems Design TechniquesLow-power high-performance VLSI design

Luis Entrena works in Radiation Effects in Electronics, VLSI and Analog Circuit Testing, Physical Unclonable Functions (PUFs) and Hardware Security, Embedded Systems Design Techniques, Low-power high-performance VLSI design. Recorded institutional associations include Universidad Carlos III de Madrid.

193Publications
2,418Citations
25H-index

ORCID

Inclusion identifies researchers whose recorded research contributions may inform their university’s understanding of its research community. It does not rank individual research quality or establish current employment.

Selected research works

Up to 100 highly cited works; DOI links open the original research. Counts reflect the collected record, not real-time citation totals.

  1. Combinational and sequential logic optimization by redundancy addition and removal

    1995 · 141 citations

  2. Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

    2007 · 134 citations

  3. Multi-level logic optimization by redundancy addition and removal

    2002 · 123 citations

  4. Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

    2010 · 113 citations

  5. Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

    2015 · 101 citations

  6. Sequential logic optimization by redundancy addition and removal

    1993 · 84 citations

  7. New techniques for speeding-up fault-injection campaigns

    2003 · 84 citations

  8. Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

    2011 · 46 citations

  9. AKARI-X: A pseudorandom number generator for secure lightweight systems

    2011 · 45 citations

  10. Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

    2016 · 44 citations

  11. A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA

    2016 · 42 citations

  12. Partial TMR in FPGAs Using Approximate Logic Circuits

    2016 · 40 citations

  13. A Unified Environment for Fault Injection at Any Design Level Based on Emulation

    2007 · 39 citations

  14. SET Emulation Considering Electrical Masking Effects

    2009 · 38 citations

  15. Logic masking for SET Mitigation Using Approximate Logic Circuits

    2012 · 36 citations

  16. Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects

    2012 · 33 citations

  17. Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

    2010 · 32 citations

  18. An industrial environment for high-level fault-tolerant structures insertion and validation

    2002 · 31 citations

  19. Efficient Mitigation of Data and Control Flow Errors in Microprocessors

    2014 · 29 citations

  20. Cryptographically secure pseudo-random bit generator for RFID tags

    2010 · 27 citations

  21. High performance FPGA-based image correlation

    2007 · 27 citations

  22. Radiation Testing of a Multiprocessor Macrosynchronized Lockstep Architecture With FreeRTOS

    2021 · 26 citations

  23. Correlation-Based Fingerprint Matching with Orientation Field Alignment

    2007 · 25 citations

  24. On the use of embedded debug features for permanent and transient fault resilience in microprocessors

    2012 · 25 citations

  25. Partial TMR in FPGAs Using Approximate Logic Circuits

    2015 · 25 citations

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